EdgeCore-T1 is an NPU IP designed to accelerate 1.58-bit Fikra models directly in hardware. Eliminating the Von Neumann bottleneck at the edge.
REVISION 0.4 (PRE-SILICON)
Vision processing for drones and warehouse robots. Ternary weights allow for high-speed object avoidance with minimal battery drain.
Agricultural monitoring and environmental sensors. Running inference locally means no 4G data costs and works completely offline.
Handheld diagnostic tools for rural clinics. Privacy-preserving inference ensures patient data never leaves the device.
ARM Ethos-U is optimized for INT8. While powerful, it treats ternary weights as standard integers, wasting 90% of memory bandwidth. EdgeCore-T1 uses native ternary packing, achieving 5x higher effective density at a fraction of the licensing cost.
Yes. Unlike black-box IP from major vendors, our Commercial license includes full SystemVerilog source code. You can optimize the datapath for your specific sensor inputs or custom SoC fabric.
We provide free simulation licenses for verified research institutions. We only ask for citation in published papers. Contact us via the form below with your .edu email.
We provide a Python-based compiler that quantizes PyTorch models into our proprietary Ternary Instruction Set Architecture (T-ISA). A C++ runtime is provided for bare-metal or Linux environments.
Connect with the foundry team to discuss IP licensing, evaluation kits, or custom silicon integration.
Direct Engineering Contact: [email protected]